A Robust CTS algorithm using the H-Tree to minimize local skews of higher frequency targets of the SOC designs | Semantic Scholar (2024)

This paper proposes to predict roughly pre-estimated CTS results using an RTL source in which temporary logic using random buffer insertion is placed before the route process to perform optimized CTS and minimizing resources according to the RTL structure to be designed.

Two mixed-signal devices have been developed using the proposed approaches, and one of those devices (e.g., ABACUS) is part of an ESPRIT project partially funded by the European Commission.

This paper proposes an efficient buffer sizing algorithm to solve the skew optimization problem in presence of process variations, and makes a quantitative estimation of the skew distribution under Monte-Carlo SPICE simulations.

A Clock tree synthesis methodology that incorporates clustering with a previously published useful-skew clock tree synthesis technique to minimize the clock wire length is introduced.

This work proposes a method where skew minimization is mainly achieved by structured routing of clock nets, and shows that with this proposal, for a few real designs from industry, it could reduce the skew up to 6.5% with increase in total wire delay up to 1.89%.

A design of a low skew clock distribution network is presented based on the TSMC 0.18µm CMOS technology and the design methodology for the chosen H-Tree clock network topology validated the 3-segment π-model.

This paper proposes a simulated annealing(SA) based algorithm along with a force-directed TSV placer to decide the selection of shutdown gates and the locations of TSVs under layout whitespace constraint to minimize 3D clock power.

This paper studies the concept of a generalized H-tree (GH-tree)—a topologically balanced tree with an arbitrary sequence of branching factors—and proposes a dynamic programming-based method to determine optimal clock power, skew, and latency, in the space of GH-tree solutions.

This paper proposes a symmetrical clock tree synthesis algorithm for top-level design, including tree architecture planning, matching, merging and embedding, and integrates buffer insertion and obstacle processing into the algorithm flow.

Effective CCTS algorithms to simultaneously reduce multicorner skew and clock divergence are proposed and Experimental results on several test-cases indicate that the methods achieve 30% reduction in the clock divergence with significantly improved multicorNER skew variance, at the cost of 2% increase in buffer area and 1% increase on wirelength.

Pseudocode listing in most of the chapters enables quicker understanding and implements various algorithms discussed in this introduction to lossless compression.